Encapsulated semiconductor package

ABSTRACT

A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No. 16/665,499, filed Oct. 28, 2019, and titled “ENCAPSULATED SEMICONDUCTOR PACKAGE,” expected to issue as U.S. Pat. No. 11,081,370; which is a continuation of U.S. patent application Ser. No. 16/427,538, filed May 31, 2019, and titled, “ENCAPSULATED SEMICONDUCTOR PACKAGE,” now U.S. Pat. No. 10,811,277; which is a continuation of U.S. patent application Ser. No. 15/634,041, filed Jun. 27, 2017, and titled “ENCAPSULATED SEMICONDUCTOR PACKAGE”; which is a continuation of U.S. patent application Ser. No. 13/679,627, filed Nov. 16, 2012, and titled “BUILDUP DIELECTRIC LAYER HAVING METALLIZATION PATTERN SEMICONDUCTOR PACKAGE FABRICATION METHOD,” now U.S. Pat. No. 9,691,635; which is a continuation of U.S. patent application Ser. No. 12/387,691, filed on May 5, 2009, and titled “BUILDUP DIELECTRIC LAYER HAVING METALLIZATION PATTERN SEMICONDUCTOR PACKAGE FABRICATION METHOD,” now U.S. Pat. No. 8,341,835; which is a divisional of U.S. patent application Ser. No. 11/497,617, filed on Aug. 1, 2006, and titled “BUILDUP DIELECTRIC AND METALLIZATION PROCESS AND SEMICONDUCTOR PACKAGE,” now U.S. Pat. No. 7,548,430; all of which are hereby incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates generally to semiconductor packaging, and more specifically, to a semiconductor package having blind vias for interconnecting a metal layer atop the semiconductor package to internal circuits of the semiconductor package.

Description of the Related Art

Semiconductor packages that provide mechanical mounting and electrical interconnection of a semiconductor die are commonly provided in ball grid array and land grid array configurations. A semiconductor die is electrically connected to a substrate with a grid array terminals disposed on the “bottom” side of the semiconductor package and solder balls are attached for connection to a system substrate, typically a printed circuit board (PCB) having lands located to attach the solder balls of the semiconductor package (referred to as ball grid array or BGA attach). Alternatively, conductive paste, a socket or “interposer” may be used to provide contacts between lands of the semiconductor package and lands on the system substrate (referred to as land grid array or LGA connection).

The above-incorporated Parent U.S. patent application discloses a top-surface mounting terminal structure for attaching a second semiconductor package or die to the top of a first semiconductor package. While the packaging density of the combined devices is increased, the location of the terminals is dictated by the design of the die or semiconductor package mounted on the first semiconductor package, which typically increases the interconnect density of the substrate in the first semiconductor package.

Also, it is often desirable to provide a metal shield cap atop a semiconductor package. Such shields are usually connected to a ground terminal or other reference voltage level by a through via extending through the semiconductor package to one or more terminals.

Therefore, it would be desirable to improve upon the techniques of the above-incorporated parent U.S. patent application to provide a semiconductor package and a method of manufacturing such a semiconductor package that facilitates stacking of grid arrays and other components while reducing interconnect densities in the semiconductor package and increases flexibility of design. It would further be desirable to improve the techniques of the above-incorporated parent U.S. patent application to provide a semiconductor package and method of manufacture that provides a metal shield cap without requiring additional through vias.

SUMMARY OF THE INVENTION

In accordance with one embodiment, a method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias.

A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup dielectric layer. The laser-ablated artifacts in the first buildup dielectric layer are filled with a first metal layer to form a first electrically conductive pattern in the first buildup dielectric layer. The operations of forming a buildup dielectric layer, forming laser-ablated artifacts in the buildup dielectric layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

These and other features of the present invention will be more readily apparent from the detailed description set forth below taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1H are pictorial diagrams depicting stages in preparation of a semiconductor package in accordance with an embodiment of the present invention;

FIGS. 2A-2C are pictorial diagrams depicting further stages in assembly of a semiconductor package in accordance with another embodiment of the present invention;

FIG. 2D is a pictorial diagram depicting a semiconductor package in accordance with another embodiment;

FIG. 3A is a pictorial diagram depicting a semiconductor package in accordance with another embodiment of the present invention;

FIGS. 3B-3C are pictorial diagrams depicting stages in fabrication of a semiconductor package in accordance with yet another embodiment of the present invention;

FIG. 4 is a pictorial diagram of an assembly 400 during the fabrication of a plurality of semiconductor packages in accordance with one embodiment of the present invention;

FIGS. 5, 6, 7, 8, and 9 are pictorial diagrams of the assembly of FIG. 4 at further stages of fabrication in accordance with various embodiments of the present invention; and

FIG. 10 is a pictorial diagram of a semiconductor package in accordance with another embodiment of the present invention.

In the following description, the same or similar elements are labeled with the same or similar reference numbers.

DETAILED DESCRIPTION

In accordance with one embodiment, referring to FIG. 4 , a method of manufacturing a semiconductor package 410A includes mounting and electrically connecting a semiconductor die 16 to a substrate 14C. Semiconductor die 16 and substrate 14C are encapsulated in an assembly encapsulant 412 to form an encapsulation 12D, encapsulation 12D being a portion of assembly encapsulant 412.

Via holes are laser-ablated through encapsulation 12D and conductive material is deposited within via holes to form vias 22A, 22B, 22C.

Referring now to FIG. 5 , a first buildup dielectric layer 502 is formed on encapsulation 12D. Laser-ablated artifacts 504 are laser-ablated in first buildup dielectric layer 502.

Referring now to FIGS. 5 and 6 together, laser-ablated artifacts 504 in first buildup dielectric layer 502 are filled with a first metal layer 602 to form a first electrically conductive pattern 604 in first buildup dielectric layer 502. As shown in FIGS. 7 and 8 , the operations of forming a buildup dielectric layer, forming laser-ablated artifacts in the buildup dielectric layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

More particularly, in accordance with the present invention, a semiconductor package and a method for manufacturing a semiconductor package that include a metal layer formed atop a semiconductor package encapsulation and connected to an internal substrate of the semiconductor package by blind vias and/or terminals on the bottom side of the encapsulation by through vias is presented.

While the exemplary embodiments depict ball grid array packages, it will be understood by those skilled in the art, that the techniques in accordance with the present invention can be extended to other types of semiconductor packages. The exemplary embodiments also show wirebond die connections within the semiconductor package, but it will be understood that any type of internal die and die mounting can be used within the semiconductor package embodiments of the present invention.

Referring now to FIG. 1A, a semiconductor package 10A for forming a semiconductor package in accordance with an embodiment of the invention and corresponding to a first illustrated step of manufacture is depicted. Semiconductor package 10A is in the form of a ball grid array (BGA) or land grid array (LGA) package as is commonly known in the art, except that particular circuit features are positioned for providing vias to the top side of semiconductor package 10A in subsequent manufacturing steps, so that connections may be made to features to be formed in subsequent steps.

Semiconductor package 10A includes a die 16 mounted to a substrate 14A that includes lands 18 to which solder ball terminals may be attached or that may be connected with a conductive paste to form a LGA mounted semiconductor package. Encapsulation 12A surrounds die 16 and substrate 14A, although substrate 14A may alternatively be exposed on a bottom side of semiconductor package 10A. Electrical connections 15, sometimes called bond pads, of die 16 are connected to circuit patterns 17 on substrate 14A via wires 19, but the type of die mounting is not limiting, but exemplary and other die mounting types may be used such as flip-chip die mounting. Additionally, while substrate 14A is depicted as a film or laminate-type mounting structure, lead frame and other substrate technologies may be used within the structures of the present invention.

Referring now to FIG. 1B, a first modification to semiconductor package 10A that illustrates a second step in the manufacturing process to form semiconductor package 10B is shown. Semiconductor package 10B includes a plurality of via holes 20A, 20B and 20C laser-ablated through encapsulation 12A of FIG. 1A to form encapsulation 12B and substrate 14B. While only three via holes are shown, many via holes may be provided. The three via holes shown and as disclosed in the above-incorporated parent U.S. patent application illustrate the three different types of via holes that may be provided through control of laser energy and exposure time. The first via hole type, illustrated as via 20A, is fabricated by laser-ablating either completely through semiconductor package 10D or by laser-ablating through encapsulation 12A to the top side of lands 18, so that a connection is provided from the top side of semiconductor package 10B to the bottom side of semiconductor package 10B when the via is filled. If via 20A is ablated completely through, then the corresponding land 18 is provided by the bottom surface of a via formed in hole 20A.

The next type of via hole is provided by laser-ablating through encapsulation 12A to reach circuit pattern 17 so that connection may be made through substrate 14A circuit patterns to die 16 electrical terminals, to lands 18 or both. The last type of via is provided by laser-ablating through encapsulation 12A to reach electrical connections 15 of die 16 so that direct connection to the circuits of die 16 can be made from a piggybacked semiconductor package. Each of via holes 20A, 20B and 20C is depicted as a via hole having a conical cross-section, which is desirable for providing uniform plating current density during a plating process. However, via holes 20A, 20B and 20C may alternatively be made cylindrical in shape if the advantage of cylindrical cross-section is not needed, for example if a conductive paste is used to fill the via holes.

Referring now to FIG. 1C, a semiconductor package step 10C is illustrated. Conductive material applied within via holes 20A, 20B and 20C to form conductive vias 22A, 22B and 22C through encapsulation 12C and optionally substrate 14C for vias that are formed completely through substrate 14C. The conductive material used to form vias 22A, 22B and 22C may be electroplated or electro-less plated metal, conductive paste such as copper or silver epoxy compounds, or a low melting temperature high-wicking solder alloy such as SUPER SOLDER.

Referring now to FIG. 1D, a next step of preparation of a semiconductor package 10D is illustrated. Channels 24 are laser-ablated in the top surface of encapsulation 12C to form encapsulation 12D. Channels 24 may define circuit traces, terminals and other features that either provide complete interconnection at the top surface of encapsulation 12D or connect top-side features such as circuit traces and terminals to one or more of vias 22A, 22B and 22C.

Next, as shown in FIG. 1E, channels 24 are filled to provide a metal layer 26 in a semiconductor package step 10E. Channels 24 may be filled by electroplating, filling with conductive paste with planarization if required, or electro-less plating after treating channels 24 with an activating compound. Further, the top surface of encapsulation 12D may be overplated or over-pasted and then etched to isolate the circuit features of metal layer 26.

After formation of metal layer 26, plating 28 may be applied as shown in FIG. 1F, yielding semiconductor package step 10F to protect the surface of metal layer and/or to prepare terminal areas defined by the top surface of metal layer 26 for further processing such as wire bond attach or soldering.

Then, as shown in FIG. 1G, a solder mask 30 may be applied over the top of encapsulation 12D and portions of the metal layer 26, yielding semiconductor package step 10G. Solder mask 30 is useful in operations where reflow solder operations will be used to attach components to metal layer 26.

Solder balls 34 may be attached to bottom-side terminals 18 of semiconductor package step 10G to yield a completed ball-grid-array (BGA) package 10H that is ready for mounting on a circuit board or other mounting location. Alternatively, as with all depicted final semiconductor packages described herein below, the step illustrated in FIG. 1H may be omitted and bottom side terminals 18 plated, yielding a land-grid-array (LGA) package.

A “tinning” coat of solder 32 may be applied to the top side of semiconductor package 10H as illustrated by FIG. 2A to prepare for mounting of top side components. The solder may be selectively applied to only solder mounting terminal areas via a mask.

Next, components are mounted on the top side of semiconductor package 10H and attached to metal layer 26 as illustrated in FIG. 28 . It will be apparent that the steps of attaching solder balls depicted in FIG. 1H can be performed after this step and that in general, various steps in formation of structures above encapsulation 12D may be performed at different times. FIG. 28 illustrates mounting of another semiconductor die 16A that is wire-bonded via wires 19A to plated terminals of metal layer 26 and also mounting of discrete surface-mount components 36 via reflow soldering.

After attachment and interconnection of die 16A, as shown in FIG. 2C, a second encapsulation 12E may be applied over die 16A, wires 19A and part of the top surface, sometimes called principal surface, of encapsulation 12D to form a completed assembly.

Another alternative embodiment of the present invention is shown in FIG. 2D. In FIG. 2D, another semiconductor package 38 may be ball-mounted to terminals formed on metal layer 26. The depicted embodiment provides for redistribution of terminals at virtually any position atop semiconductor package 10H2, since metal layer 26 can provide routing of circuits from vias such as 22A-C to solder balls 34A at virtually any position atop semiconductor package 10H2.

FIG. 3A illustrates another embodiment of the present invention that includes a metal layer 50 that provides a shield cap for semiconductor package 10I. Metal layer 50 may be electro-less plated atop encapsulation 12C (See FIGS. 1A-1C for formation steps prior to FIG. 3A) by applying a seed layer or may be paste screened to form metal layer 50. Metal layer 50 may be solid layer, or a continuous pattern such as a mesh screen to reduce separation and required metal to improve the plating process. Metal layer 50 is electrically connected to vias 22A and/or 22B to provide a return path for the shield.

FIG. 3B illustrates another shield embodiment of the present invention. A shield cavity is laser-ablated in the top surface of encapsulation 12E to form a semiconductor package step 10J having a cavity 24A. Cavity 24A is then filled to form a metal shield layer 50A as shown in FIG. 3C. Metal layer 50A may be applied by paste screening or plating (and possible subsequent etching process) to yield a shield that is contained within the sides of semiconductor package 10K.

FIG. 4 is a pictorial diagram of an assembly 400 during the fabrication of a plurality of semiconductor packages 410 in accordance with one embodiment of the present invention. Referring now to FIGS. 1E and 4 together, assembly 400 of FIG. 4 includes a plurality of semiconductor packages 410 integrally connected together. Each semiconductor package 410 of assembly 400 is substantially identical to semiconductor package 10E of FIG. 1E, and semiconductor packages 410 are simply relabeled for clarity of discussion. Only the significant differences between assembly 400 and semiconductor package 10E are discussed below.

Illustratively, assembly 400 includes an assembly substrate 414 comprising a plurality of substrates 14C integrally connected together. Substrates 14C are substantially similar to substrate 14C illustrated in FIG. 1C.

Further, assembly 400 includes an assembly encapsulant 412, e.g., a single integral layer of encapsulant encapsulating assembly substrate 414, corresponding to a plurality of the encapsulations 12D illustrated in FIG. 1E. Assembly 400 of FIG. 4 is fabricated in a manner similar to that discussed above with regards to semiconductor package 10E of FIG. 1E, the discussion of which is herein incorporated by reference.

Referring now to FIG. 4 , assembly 400 includes a plurality of semiconductor packages 410 as set forth above. Illustratively, semiconductor packages 410 are delineated from one another by singulation streets 430. Semiconductor packages 410 include a first semiconductor package 410A, which is representative of all of the semiconductor packages 410.

FIG. 5 is a pictorial diagram of assembly 400 at a further stage of fabrication in accordance with one embodiment of the present invention. Referring now to FIG. 5 , a first assembly buildup dielectric layer 502 is formed on the principal surface 412P of assembly encapsulant 412.

Buildup dielectric layer 502 is an electrically insulating material. Illustratively, buildup dielectric layer 502 is epoxy molding compound (EMC) molded on principal surface 412P of assembly encapsulant 412. In another example, buildup dielectric layer 502 is a liquid encapsulant that has been cured. In yet another example, buildup dielectric layer 502 is a single sided adhesive dielectric layer which is adhered on principal surface 412P of assembly encapsulant 412. Although various examples of buildup dielectric layer 502 are set forth, the examples are not limiting, and it is to be understood that other dielectric materials can be used to form buildup dielectric layer 502.

Laser-ablated artifacts 504, e.g., openings, are formed in buildup dielectric layer 502 using laser ablation in one embodiment. Illustratively, laser-ablated artifacts 504 include via holes 506 and channels 508. Laser-ablated artifacts 504 extend through buildup dielectric layer 502 and expose portions of metal layer 26.

FIG. 6 is a pictorial diagram of assembly 400 at a further stage of fabrication in accordance with one embodiment of the present invention. Referring now to FIGS. 5 and 6 together, a metal layer 602 is formed and fills laser-ablated artifacts 504. More generally, laser-ablated artifacts 504 are filled with metal layer 602, e.g., an electrically conductive material such as copper. Illustratively, copper is plated and reduced to fill laser-ablated artifacts 504.

Filling laser-ablated artifacts 504 creates an electrically conductive pattern 604 within first buildup dielectric layer 502. Illustratively, via holes 506 and channels 508 (FIG. 5 ) are filled with metal layer 602 to form electrically conductive vias 606 and traces 608, respectively, within first buildup dielectric layer 502.

Vias 606 and traces 608 are electrically connected to the pattern of metal layer 26. In one example, vias 606 are vertical conductors extending through buildup dielectric layer 502 in a direction substantially perpendicular to the plane formed by a principal surface 502P of buildup dielectric layer 502. Traces 608 are horizontal conductors extending parallel to the plane formed by a principal surface 502P of buildup dielectric layer 502. Traces 608 extend entirely through buildup dielectric layer 502 as shown in FIG. 6 . However, in another embodiment, traces 608 are formed in buildup dielectric layer 502 at principal surface 502P and a portion of buildup dielectric layer 502 remains between traces 608 and assembly encapsulant 412. Although vias 606 and traces 608 are set forth, in light of this disclosure, those of skill in the art will understand that other electrically conductive structures can be formed in electrically conductive pattern 604. Illustratively, solder ball pads or SMT pads are formed in electrically conductive pattern 604.

Further, it is understood that the operations of forming a buildup dielectric layer, forming laser-ablated artifacts in the buildup dielectric layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution. Such an example is set forth below in reference to FIGS. 7 and 8 .

FIG. 7 is a pictorial diagram of assembly 400 at a further stage of fabrication in accordance with one embodiment of the present invention. Referring now to FIG. 7 , a second buildup dielectric layer 702 is formed on principal surface 502P of first buildup dielectric layer 502.

Buildup dielectric layer 702 is an electrically insulating material. In one embodiment, buildup dielectric layer 702 is formed of the same material and in a similar manner as buildup dielectric layer 502, and so formation of buildup dielectric layer 702 is not discussed in detail.

Laser-ablated artifacts 704, e.g., openings, are formed in buildup dielectric layer 702 using laser ablation in one embodiment. Illustratively, laser-ablated artifacts 704 include via holes, channels, solder ball pad openings and/or SMT pad openings. Laser-ablated artifacts 704 extend through buildup dielectric layer 702 and expose portions of metal layer 602.

FIG. 8 is a pictorial diagram of assembly 400 at a further stage of fabrication in accordance with one embodiment of the present invention. Referring now to FIGS. 7 and 8 together, a metal layer 802 is formed and fills laser-ablated artifacts 704. More generally, laser-ablated artifacts 704 are filled with metal layer 802, e.g., an electrically conductive material 802 such as copper. Illustratively, copper is plated and reduced to fill laser-ablated artifacts 704.

Filling laser-ablated artifacts 704 creates an electrically conductive pattern 804. Illustratively, electrically conductive pattern 804 includes electrically conductive vias, traces, solder ball pads, and/or SMT pads. Electrically conductive pattern 804 is electrically connected to electrically conductive pattern 604 through buildup dielectric layer 702.

FIG. 9 is a pictorial diagram of assembly 400 at a further stage of fabrication in accordance with one embodiment of the present invention. Referring now to FIGS. 8 and 9 together, assembly 400 is singulated along singulation streets 430 thus forming a plurality of individual semiconductor packages 410 as shown in FIG. 9 . Each semiconductor packages 410 includes an encapsulation 12D, a substrate 14C, a first buildup dielectric layer 902, and a second buildup dielectric layer 904. Encapsulation 12D is a portion of assembly encapsulant 412. Substrate 14C is a portion of assembly substrate 414. First buildup dielectric layer 902 is a portion of assembly buildup dielectric layer 502. Finally, second buildup dielectric layer 904 is a portion of assembly buildup dielectric layer 702.

As shown in FIG. 9 , for each semiconductor package 410, sides 14S, 12S, 902S, 9045 of substrate 14C, encapsulation 12D, first buildup dielectric layer 902, second buildup layer 904, respectively, are flush with one another, i.e., are substantially coplanar and in the same plane.

Although the formation of a plurality of individual semiconductor packages 410 using assembly 400 is set forth above, in light of this disclosure, those of skill the art will understand that semiconductor packages 410 can be formed individually, if desired.

FIG. 10 is a pictorial diagram of a semiconductor package 1010 in accordance with another embodiment of the present invention. Semiconductor package 1010 of FIG. 10 is similar to semiconductor package 410A of FIG. 9 and only the significant differences are discussed below.

Semiconductor package 1010 includes a first buildup dielectric layer 902A and a second buildup dielectric layer 904A. First buildup dielectric layer 902A and second buildup dielectric layer 904A of semiconductor package 1010 of FIG. 10 are similar to first buildup dielectric layer 902 and second buildup dielectric layer 904 of semiconductor package 410 of FIG. 9 , respectively. Only the significant differences between buildup dielectric layers 902A, 904A and buildup dielectric layers 902, 904 are discussed below.

Referring now to FIG. 10 , first buildup dielectric layer 902A entirely encloses encapsulation 12D. More particularly, first buildup dielectric layer 902A forms a cap that entirely encloses encapsulation 12D. First buildup dielectric layer 902A is formed on and directly contacts the principal surface 12P and sides 12S of encapsulation 12D. Further, first buildup dielectric layer 902A contacts the upper surface of substrate 14C directly adjacent encapsulation 12D.

First buildup dielectric layer 902A includes a horizontal portion 1002 and sidewalls 1004. Horizontal portion 1002 contacts principal surface 12P of encapsulation 12D. Sidewalls 1004 extend perpendicularly from horizontal portion 1002 to substrate 14C and contact sides 12S of encapsulation 12D.

Similarly, second buildup dielectric layer 904A entirely encloses first buildup dielectric layer 902A. More particularly, second buildup dielectric layer 904A forms a cap that entirely encloses first buildup dielectric layer 902A. Second buildup dielectric layer 904A is formed on and directly contacts the horizontal portion 1002 and sidewalls 1004 of first buildup dielectric layer 902A. Further, second buildup dielectric layer 904A contacts the upper surface of substrate 14C directly adjacent first buildup dielectric layer 902A.

Second buildup dielectric layer 904A includes a horizontal portion 1022 and sidewalls 1024. Horizontal portion 1022 contacts horizontal portion 1002 of first buildup dielectric layer 902A. Sidewalls 1024 extend perpendicularly from horizontal portion 1022 to substrate 14C and contact sidewalls 1004 of first buildup dielectric layer 902A.

Semiconductor packages 410, 1010 (FIGS. 9, 10 ) can be further processed. Illustratively, plating and solder masks similar to plating 28 of FIG. 1F and solder mask 30 of FIG. 1G are formed. Solder balls are attached to bottom-side terminals 18 to yield a completed ball-grid-array (BGA) package that is ready for mounting on a circuit board or other mounting location. Formation of solder balls is similar to formation of solder balls 34 as illustrated in FIG. 1H and discussed above and so is not repeated here. Alternatively, solder balls are not formed, yielding a land-grid-array (LGA) package.

A “tinning” coat of solder may be applied to the metal layer 802 to prepare for mounting of top side components. The solder is similar to solder 32 as illustrated in FIG. 2A and discussed above and so is not repeated here. The solder may be selectively applied to only solder mounting terminal areas via a mask.

Next, components are mounted on the top surface of semiconductor package 410, 1010 and attached to metal layer 802 in a manner similar to that illustrated in FIGS. 2C, 2D, and so is not repeated here. By forming electrically conductive patterns in successive buildup dielectric layers, the pattern of vias 22A, 22B, 22C is redistributed into the desired footprint (layout) of the top most electrically conductive pattern, e.g., electrically conductive pattern 804. Specifically, the footprint of electrically conductive pattern 804 is optimized for attachment of component(s) on the top surface of semiconductor packages 410, 1010. Conversely, the pattern of vias 22A, 22B, 22C is largely dictated by the layout of lands 18, circuit pattern 17 and electrical conductors 15.

The drawings and the forgoing description give examples of the present invention. The scope of the present invention, however, is by no means limited by these specific examples. Numerous variations, whether explicitly given in the specification or not, such as differences in structure, dimension, and use of material, are possible. The scope of the invention is at least as broad as given by the following claims. 

What is claimed is:
 1. An integrated circuit package comprising: a signal redistribution structure (SRS) comprising a first SRS side, and a second SRS side opposite the first SRS side, the SRS comprising: a first conductive layer comprising a first trace; a first dielectric layer (DL) that directly contacts and laterally surrounds the first trace, the first dielectric layer comprising a first DL side, a second DL side opposite the first DL side, and a lateral DL side that extends between the first DL side and the second DL side; a second conductive layer comprising a second trace; and a third conductive layer comprising a conductive via; an integrated circuit die comprising: a first die side, a second die side opposite the first die side, and a lateral die side that extends between the first die side and the second die side; and a die pad at the second die side, where: the first die side faces away from the SRS; the second die side faces the SRS; and the second die side is coupled to the first SRS side; and an encapsulating structure that laterally surrounds at least the integrated circuit die and the first dielectric layer of the SRS, and directly contacts the lateral DL side.
 2. The integrated circuit package of claim 1, wherein the encapsulating structure vertically and horizontally spans an entirety of the integrated circuit die and an entirety of the signal redistribution structure (SRS).
 3. The integrated circuit package of claim 1, wherein: the encapsulating structure directly contacts the lateral die side; the encapsulating structure directly contacts the second die side; and the encapsulating structure directly contacts the first SRS side.
 4. The integrated circuit package of claim 1, wherein the encapsulating structure comprises an epoxy molding compound.
 5. The integrated circuit package of claim 1, wherein the encapsulating structure comprises: a first encapsulating part that laterally surrounds the integrated circuit die and directly contacts the lateral die side; and a second encapsulating part that laterally surrounds the first dielectric layer of the SRS and directly contacts the lateral DL side.
 6. The integrated circuit package of claim 1, wherein the signal redistribution structure (SRS) comprises a ball pad at the second SRS side.
 7. The integrated circuit package of claim 1, wherein the signal redistribution structure (SRS) comprises: a first ball pad at the second SRS side and positioned within a footprint of the integrated circuit die; and a second ball pad at the second SRS side and positioned outside of the footprint of the integrated circuit die.
 8. The integrated circuit package of claim 1, wherein the encapsulating structure comprises a planar lateral side surface that runs vertically and completely between a first vertical level that corresponds to the first die side and a second vertical level that corresponds to the second SRS side.
 9. An integrated circuit package comprising: a signal redistribution structure (SRS) comprising a first SRS side, and a second SRS side opposite the first SRS side, the SRS comprising: a first conductive layer comprising a first trace; a first dielectric layer (DL) that directly contacts and laterally surrounds the first trace, the first dielectric layer comprising a first DL side, a second DL side opposite the first DL side, and a lateral DL side that extends between the first DL side and the second DL side; a second conductive layer comprising a second trace; and a third conductive layer comprising a plurality of pads; an integrated circuit die comprising: a first die side, a second die side opposite the first die side, and a lateral die side that extends between the first die side and the second die side; and a die pad at the second die side, where the second die side faces and is coupled to the first SRS side; and an encapsulating layer comprising a first encapsulating layer side that faces a same direction as the first die side, a second encapsulating layer side that faces a same direction as the second die side, and a lateral encapsulating layer side that extends between the first encapsulating layer side and the second encapsulating layer side, where: the encapsulating layer directly contacts the lateral DL side; each of the pads of the third conductive layer comprises an exposed pad side that faces a same direction as the second encapsulating layer side and is exposed from the encapsulating layer at the second SRS side; and the encapsulating layer laterally surrounds the pads of the third conductive layer.
 10. The integrated circuit package of claim 9, wherein a portion of the second encapsulating layer side is substantially at a same vertical level as the exposed pad sides of the pads of the third conductive layer.
 11. The integrated circuit package of claim 9, wherein the encapsulating layer vertically and horizontally spans an entirety of the integrated circuit die and an entirety of the signal redistribution structure (SRS).
 12. The integrated circuit package of claim 9, wherein the encapsulating layer comprises an epoxy molding compound.
 13. The integrated circuit package of claim 9, wherein the encapsulating layer directly contacts each of the pads of the third conductive layer.
 14. The integrated circuit package of claim 9, wherein: a first pad of the plurality of pads of the third conductive layer is positioned at the second SRS side and within a footprint of the integrated circuit die; and a second pad of the plurality of pads of the third conductive layer is positioned at the second SRS side and outside of the footprint of the integrated circuit die.
 15. The integrated circuit package of claim 9, wherein the lateral encapsulating layer side comprises a planar surface that runs vertically and completely between a first vertical level that corresponds to the first die side and a second vertical level that corresponds to the second SRS side.
 16. An integrated circuit package comprising: a signal redistribution structure (SRS) comprising a first SRS side, and a second SRS side opposite the first SRS side, the SRS comprising: a first conductive layer comprising a first trace; a first dielectric layer (DL) that directly contacts and laterally surrounds the first trace, the first dielectric layer comprising a first DL side, a second DL side opposite the first DL side, and a lateral DL side that extends between the first DL side and the second DL side; a second conductive layer comprising a second trace; and a third conductive layer comprising a conductive via; an integrated circuit die comprising: a first die side, a second die side opposite the first die side, and a lateral die side that extends between the first die side and the second die side; and a die pad at the second die side, where the second die side faces and is coupled to the first SRS side; and an encapsulating layer comprising a first encapsulating layer side that faces a same direction as the first die side, a second encapsulating layer side that faces a same direction as the second die side, and a lateral encapsulating layer side that extends between the first encapsulating layer side and the second encapsulating layer side, where a portion of the second encapsulating layer side around a perimeter of the second SRS side is exposed at an exterior of the integrated circuit package.
 17. The integrated circuit package of claim 16, wherein a portion of the second encapsulating layer side is substantially at a same vertical level as the second SRS side.
 18. The integrated circuit package of claim 16, wherein the encapsulating layer vertically and horizontally spans an entirety of the integrated circuit die and an entirety of the signal redistribution structure (SRS).
 19. The integrated circuit package of claim 16, wherein the encapsulating layer comprises an epoxy molding compound.
 20. The integrated circuit package of claim 16, wherein the lateral encapsulating layer side comprises a planar surface that runs vertically and completely between a first vertical level that corresponds to the first die side and a second vertical level that corresponds to the second SRS side. 